Clock signals comprise both rising and falling edges. A rising edge may rise at a different latency than a falling edge and these differences in latency may be corrected by the use of one or more delay tuners. In conventional systems, large differences between rise and fall latency may require the use of numerous tuners, which may result in a large fixed amount of latency and also an increase in required power.
Some existing commercial designs simply accept the fixed latency penalty of an extended fine delay pipeline. In one instance, a delay fine tuner stage might have twice the fixed latency as variable latency, and a particular product requirement might mandate several stages in series.